Computer systems have historically included at least one main electronics enclosure which is arranged to have mounted therein a plurality of circuit boards. The circuit boards, in turn, typically include a large number of integrated circuits (ICs) or so called "chips". With continuing advances in circuit integration and miniaturization, more and more of the individual single purpose chips are being integrated into fewer "full function" chips which include more functionality in less space.
As chip densities continue to increase, more of the computer system functions such as audio, video, and graphics, which have heretofore been normally coupled to a processor at the card level, are now being integrated onto the same IC as the system processor. With this increase in the number of functions being combined in a single IC, the bandwidth requirements of on-chip busses have also increased. As a result, several "on-chip" bus architectures are being developed to address the bandwidth requirements of the new "system-on-a-chip" design.
In one such processor local bus or PLB architecture, the address transfers, the read transfers and the write transfers are decoupled from one another which allows for the overlapping of read and write data transfers. As a result a very high bandwidth is attained since two data transfers, i.e. a read data transfer and a write data transfer, can be performed simultaneously.
In such systems, the decoupling of the address, read and write data transfers is accomplished via the use of three separate busses and a unique transfer acknowledge signal for each bus. In addition to the transfer acknowledge signals, a pair of "transfer complete" signals are used to indicate the completion of data transfers across the read and write data busses. At the completion of a read data transfer, a "read complete" signal is asserted by the slave device to indicate to the arbiter that the current data transfer has been completed, and the bus is now available for a new data transfer. In response to the assertion of the read complete signal, the arbiter will allow the address for a new read data transfer to be presented to the slave devices.
Similarly, at the completion of a write data transfer, a "write complete" signal is asserted by the slave to indicate to the arbiter that the current data transfer has been completed and the bus is now available for a new transfer. In response to the assertion of the write complete signal, the arbiter will allow the address for a new write data transfer request to be presented to the slave devices.
Many memory controllers which are being designed to couple with PLB systems, are devices which have a large initial latency or access time for the first data access. With the current PLB architecture, the non-pipelined nature of the address bus does not allow for the overlap of the initial access latency with a previous data transfer in the same direction. For example, in a given system, a memory controller is attached to an SDRAM memory which may have an initial access of six clock cycles. The memory controller in the example is designed such that while one bank of SDRAM is being accessed, a second access can be started in order to reduce the initial latency associated with waiting for the first access to be completed. With the current PLB architecture, when there are two back-to-back requests to read a word of data, the address valid (AValid) signal for the second read transfer is not asserted until the read complete (RdComp) signal is asserted for the first read transfer, indicating that the first read transfer will complete in the following cycle. Thus the second read transfer from the memory controller is not started until the cycle following the assertion of the RdComp signal for the first read transfer. Due to the pipelined nature of an SDRAM memory device, if the AValid signal, the address bus, and the transfer qualifiers for the second read transfer had been asserted in the cycle following the AValid for the first read transfer, then the initial latency for the second read transfer could have been overlapped with the initial latency or data transfer for the first transfer thus improving the overall performance of the system in accomplishing the data transfers.
However, if a second read request is presented to the memory controller prior to the memory controller transferring all of the data for the first read request, then a way is required for the memory controller to guarantee that the memory controller will complete the transfer of data for the first and second requests in the order in which the requests were presented. Furthermore, if a second read request is presented to a second memory controller on the PLB prior to the first memory controller transferring all of the data for the first read transfer, then a way to prevent a collision between the data being transferred by the first controller and the data being transferred by the second controller must also be provided since data for both transfers must share the use of the one PLB read data bus.
Accordingly, there is a need for an enhanced method and processing apparatus which is effective to allow for address pipelining for both read and write operations on a PLB bus system.